54 search results - page 1 / 11 » Coverage Metrics for Formal Verification |
CHARME
2003
Springer
13 years 8 months ago
2003
Springer
In formal verification, we verify that a system is correct with respect to a specification. Even when the system is proven to be correct, there is still a question of how complete ...
DAC
2002
ACM
14 years 5 months ago
2002
ACM
This paper presents novel uses of functional interface specifications for verifying RTL designs. We demonstrate how a simulation environment, a correctness checker, and a function...
IFIP
2001
Springer
13 years 9 months ago
2001
Springer
— Semi-formal verification based on symbolic simulation offers a good compromise between formal model checking and numerical simulation. The generation of functional test vector...
DAC
1998
ACM
13 years 8 months ago
1998
ACM
—Functional simulation is still the primary workhorse for verifying the functional correctness of hardware designs. Functional verification is necessarily incomplete because it i...
ICCAD
1996
IEEE
13 years 8 months ago
1996
IEEE
Functional simulation is the most widely used method for design verification. At various levels of abstraction, e.g., behavioral, register-transfer level and gate level, the design...