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DAC
2003
ACM
9 years 10 months ago
Coverage directed test generation for functional verification using bayesian networks
Functional verification is widely acknowledged as the bottleneck in the hardware design cycle. This paper addresses one of the main challenges of simulation based verification (or...
Shai Fine, Avi Ziv
IFIP
2001
Springer
9 years 1 months ago
Functional Test Generation using Constraint Logic Programming
— Semi-formal verification based on symbolic simulation offers a good compromise between formal model checking and numerical simulation. The generation of functional test vector...
Zhihong Zeng, Maciej J. Ciesielski, Bruno Rouzeyre
CODES
2008
IEEE
8 years 11 months ago
Specification-based compaction of directed tests for functional validation of pipelined processors
Functional validation is a major bottleneck in microprocessor design methodology. Simulation is the widely used method for functional validation using billions of random and biase...
Heon-Mo Koo, Prabhat Mishra
DATE
2004
IEEE
174views Hardware» more  DATE 2004»
9 years 1 months ago
Graph-Based Functional Test Program Generation for Pipelined Processors
Functional verification is widely acknowledged as a major bottleneck in microprocessor design. While early work on specification driven functional test program generation has prop...
Prabhat Mishra, Nikil Dutt
DATE
2007
IEEE
155views Hardware» more  DATE 2007»
9 years 3 months ago
Design fault directed test generation for microprocessor validation
Functional validation of modern microprocessors is an important and complex problem. One of the problems in functional validation is the generation of test cases that has higher p...
Deepak Mathaikutty, Sandeep K. Shukla, Sreekumar V...
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