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» Crosstalk Reduction by Transistor Sizing
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ASPDAC
1999
ACM
143views Hardware» more  ASPDAC 1999»
13 years 9 months ago
Crosstalk Reduction by Transistor Sizing
In this paper we consider transistor sizing to reduce crosstalk. First, crosstalk noise dependency on wire width, wire spacing, driver and receiver sizes are discussed, and valida...
Tong Xiao, Malgorzata Marek-Sadowska
ICCD
2001
IEEE
213views Hardware» more  ICCD 2001»
14 years 2 months ago
Analysis and Reduction of Capacitive Coupling Noise in High-Speed VLSI Circuits
Abstract-- Scaling the minimum feature size of VLSI circuits to sub-quarter micron and its clock frequency to 2GHz has caused crosstalk noise to become a serious problem, that degr...
Payam Heydari, Massoud Pedram
ICCAD
2004
IEEE
115views Hardware» more  ICCAD 2004»
14 years 2 months ago
Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation
Abstract— This paper presents a post-route, timingconstrained gate-sizing algorithm for crosstalk reduction. Gate-sizing has emerged as a practical and feasible method to reduce ...
Debjit Sinha, Hai Zhou
ISPD
1998
ACM
244views Hardware» more  ISPD 1998»
13 years 9 months ago
Analysis, reduction and avoidance of crosstalk on VLSI chips
As chip size and design density increase, coupling effects (crosstalk) between signal wires become increasingly critical to on–chip timing and even functionality. A method is pr...
Tilmann Stöhr, Markus Alt, Asmus Hetzel, J&uu...
ICCD
2002
IEEE
137views Hardware» more  ICCD 2002»
14 years 2 months ago
Combining Dual-Supply, Dual-Threshold and Transistor Sizing for Power Reduction
Multiple supply voltages, multiple transistor thresholds and transistor sizing could be used to reduce the power dissipation of digital blocks. This paper presents a framework for...
Stephanie Augsburger, Borivoje Nikolic