Sciweavers

60 search results - page 12 / 12
» Crosstalk Reduction in Area Routing
Sort
View
ICCAD
2002
IEEE
227views Hardware» more  ICCAD 2002»
14 years 2 months ago
Generic ILP versus specialized 0-1 ILP: an update
Optimized solvers for the Boolean Satisfiability (SAT) problem have many applications in areas such as hardware and software verification, FPGA routing, planning, etc. Further use...
Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Kare...
FPGA
1999
ACM
139views FPGA» more  FPGA 1999»
13 years 10 months ago
Trading Quality for Compile Time: Ultra-Fast Placement for FPGAs
The demand for high-speed FPGA compilation tools has occurred for three reasons: first, as FPGA device capacity has grown, the computation time devoted to placement and routing h...
Yaska Sankar, Jonathan Rose
CONEXT
2007
ACM
13 years 9 months ago
Fair and efficient scheduling in data ferrying networks
Data-ferrying disconnection-tolerant networks allow remote rural areas to access the Internet at very low cost, making them viable alternatives to more expensive access technologi...
Shimin Guo, Srinivasan Keshav
JGAA
2006
100views more  JGAA 2006»
13 years 5 months ago
Orthogonal Hypergraph Drawing for Improved Visibility
Visualization of circuits is an important research area in electronic design automation. One commonly accepted method to visualize a circuit aligns the gates to layers and uses or...
Thomas Eschbach, Wolfgang Günther, Bernd Beck...
JETC
2008
127views more  JETC 2008»
13 years 4 months ago
Automated module assignment in stacked-Vdd designs for high-efficiency power delivery
With aggressive reductions in feature sizes and the integration of multiple functionalities on the same die, bottlenecks due to I/O pin limitations have become a severe issue in to...
Yong Zhan, Sachin S. Sapatnekar