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ESAS
2004
Springer
13 years 10 months ago
Secure AES Hardware Module for Resource Constrained Devices
Abstract. Low power consumption, low gate count, and high throughput are standard design criteria for cryptographic coprocessors designated for resource constrained devices such as...
Elena Trichina, Tymur Korkishko
CHES
2010
Springer
187views Cryptology» more  CHES 2010»
13 years 6 months ago
Garbled Circuits for Leakage-Resilience: Hardware Implementation and Evaluation of One-Time Programs - (Full Version)
The power of side-channel leakage attacks on cryptographic implementations is evident. Today's practical defenses are typically attack-specific countermeasures against certain...
Kimmo Järvinen, Vladimir Kolesnikov, Ahmad-Re...
FC
1997
Springer
86views Cryptology» more  FC 1997»
13 years 9 months ago
The SPEED Cipher
Abstract. SPEED is a private key block cipher. It supports three variable parameters: (1) data length — the length of a plaintext/ciphertext of SPEED can be 64, 128 or 256 bits. ...
Yuliang Zheng
WISA
2009
Springer
13 years 12 months ago
You Cannot Hide behind the Mask: Power Analysis on a Provably Secure S-Box Implementation
Power analysis has shown to be successful in breaking symmetric cryptographic algorithms implemented on low resource devices. Prompted by the breaking of many protected implementat...
J. Pan, J. I. den Hartog, Jiqiang Lu