9 search results - page 1 / 2 » Customizing the Datapath and ISA of Soft VLIW Processors |
HIPEAC
2007
Springer
13 years 8 months ago
2007
Springer
In this paper, we examine the trade-offs in performance and area due to customizing the datapath and instruction set architecture of a soft VLIW processor implemented in a high-den...
DAC
1999
ACM
14 years 5 months ago
1999
ACM
It is generally believed that there will be little more variety in CPU architectures, and thus the design of Instruction-set Architectures (ISAs) will have no role in the future o...
ISSS
1999
IEEE
13 years 8 months ago
1999
IEEE
This paper describes a mechanism for automatic design and synthesis of very long instruction word (VLIW), and its generalization, explicitly parallel instruction computing rocesso...
ICCAD
2001
IEEE
14 years 1 months ago
2001
IEEE
In this paper we describe a software pipelining framework, CALiBeR (Cluster Aware Load Balancing Retiming Algorithm), suitable for compilers targeting clustered embedded VLIW proc...
IPPS
2010
IEEE
13 years 2 months ago
2010
IEEE
There is building interest in using FPGAs as accelerators for high-performance computing, but existing systems for programming them are so far inadequate. In this paper we propose...