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DAC
1994
ACM
13 years 10 months ago
HSIS: A BDD-Based Environment for Formal Verification
Functional and timing verification are currently the bottlenecks in many design efforts. Simulation and emulation are extensively used for verification. Formal verification is now...
Adnan Aziz, Felice Balarin, Szu-Tsung Cheng, Ramin...
ASPDAC
2007
ACM
152views Hardware» more  ASPDAC 2007»
13 years 9 months ago
A Graph Reduction Approach to Symbolic Circuit Analysis
A new graph reduction approach to symbolic circuit analysis is developed in this paper. A Binary Decision Diagram (BDD) mechanism is formulated, together with a specially designed ...
Guoyong Shi, Weiwei Chen, C.-J. Richard Shi
DAC
2003
ACM
14 years 6 months ago
Symbolic representation with ordered function templates
Binary Decision Diagrams (BDDs) often fail to exploit sharing between Boolean functions that differ only in their support variables. In a memory circuit, for example, the function...
Amit Goel, Gagan Hasteer, Randal E. Bryant
QEST
2008
IEEE
14 years 4 days ago
Symbolic Magnifying Lens Abstraction in Markov Decision Processes
Magnifying Lens Abstraction in Markov Decision Processes ∗ Pritam Roy1 David Parker2 Gethin Norman2 Luca de Alfaro1 Computer Engineering Dept, UC Santa Cruz, Santa Cruz, CA, USA ...
Pritam Roy, David Parker, Gethin Norman, Luca de A...
CAV
1999
Springer
104views Hardware» more  CAV 1999»
13 years 10 months ago
On the Representation of Probabilities over Structured Domains
Abstract. In this paper we extend one of the main tools used in veri cation of discrete systems, namely Binary Decision Diagrams (BDD), to treat probabilistic transition systems. W...
Marius Bozga, Oded Maler