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BMCBI
2010
129views more  BMCBI 2010»
13 years 5 months ago
The LabelHash Algorithm for Substructure Matching
Background: There is an increasing number of proteins with known structure but unknown function. Determining their function would have a significant impact on understanding diseas...
Mark Moll, Drew H. Bryant, Lydia E. Kavraki
CF
2009
ACM
13 years 12 months ago
Mapping the LU decomposition on a many-core architecture: challenges and solutions
Recently, multi-core architectures with alternative memory subsystem designs have emerged. Instead of using hardwaremanaged cache hierarchies, they employ software-managed embedde...
Ioannis E. Venetis, Guang R. Gao
ISCA
1994
IEEE
117views Hardware» more  ISCA 1994»
13 years 9 months ago
Evaluating Stream Buffers as a Secondary Cache Replacement
Today's commodity microprocessors require a low latency memory system to achieve high sustained performance. The conventional high-performance memory system provides fast dat...
Subbarao Palacharla, Richard E. Kessler
SOSP
1997
ACM
13 years 6 months ago
Cashmere-2L: Software Coherent Shared Memory on a Clustered Remote-Write Network
Low-latency remote-write networks, such as DEC’s Memory Channel, provide the possibility of transparent, inexpensive, large-scale shared-memory parallel computing on clusters of...
Robert Stets, Sandhya Dwarkadas, Nikos Hardavellas...
ISCA
2010
IEEE
199views Hardware» more  ISCA 2010»
13 years 10 months ago
A case for FAME: FPGA architecture model execution
Given the multicore microprocessor revolution, we argue that the architecture research community needs a dramatic increase in simulation capacity. We believe FPGA Architecture Mod...
Zhangxi Tan, Andrew Waterman, Henry Cook, Sarah Bi...