27 search results - page 2 / 6 » DRAM Energy Management Using Software and Hardware Directed ... |
ISCA
2012
IEEE
11 years 7 months ago
2012
IEEE
Modern memory controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource...
ICCD
2005
IEEE
14 years 2 months ago
2005
IEEE
Main memory has become one of the largest contributors to overall energy consumption and offers many opportunities for power/energy reduction. In this paper, we propose a PowerAw...
ASPLOS
2010
ACM
13 years 8 months ago
2010
ACM
Power consumption and DRAM latencies are serious concerns in modern chip-multiprocessor (CMP or multi-core) based compute systems. The management of the DRAM row buffer can signif...
CODES
1999
IEEE
13 years 9 months ago
1999
IEEE
Reducing power consumption is critical in many system designs. Dynamic power management is an effective approach to decrease power without significantly degrading performance. Pow...
SIGMETRICS
2012
ACM
11 years 7 months ago
2012
ACM
The energy consumed by data centers is starting to make up a significant fraction of the world’s energy consumption and carbon emissions. A large fraction of the consumed energ...