Sciweavers

27 search results - page 2 / 6
» DRAM reliability
Sort
View
ISCAS
2003
IEEE
172views Hardware» more  ISCAS 2003»
13 years 11 months ago
Performance modeling of resonant tunneling based RAMs
Tunneling based random-access memories (TRAM’s) have recently garnered a great amount of interests among the memory designers due to their intrinsic merits such as reduced power...
Hui Zhang, Pinaki Mazumder, Li Ding 0002, Kyoungho...
CACM
2010
145views more  CACM 2010»
13 years 6 months ago
Phase change memory architecture and the quest for scalability
Memory scaling is in jeopardy as charge storage and sensing mechanisms become less reliable for prevalent memory technologies, such as dynamic random access memory (DRAM). In cont...
Benjamin C. Lee, Engin Ipek, Onur Mutlu, Doug Burg...
SIGMETRICS
2009
ACM
134views Hardware» more  SIGMETRICS 2009»
14 years 23 days ago
DRAM errors in the wild: a large-scale field study
Errors in dynamic random access memory (DRAM) are a common form of hardware failure in modern compute clusters. Failures are costly both in terms of hardware replacement costs and...
Bianca Schroeder, Eduardo Pinheiro, Wolf-Dietrich ...
ISCA
2010
IEEE
336views Hardware» more  ISCA 2010»
13 years 10 months ago
Reducing cache power with low-cost, multi-bit error-correcting codes
Technology advancements have enabled the integration of large on-die embedded DRAM (eDRAM) caches. eDRAM is significantly denser than traditional SRAMs, but must be periodically r...
Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chisht...
ISCA
2010
IEEE
305views Hardware» more  ISCA 2010»
13 years 11 months ago
Rethinking DRAM design and organization for energy-constrained multi-cores
DRAM vendors have traditionally optimized the cost-perbit metric, often making design decisions that incur energy penalties. A prime example is the overfetch feature in DRAM, wher...
Aniruddha N. Udipi, Naveen Muralimanohar, Niladris...