148 search results - page 29 / 30 » DRAMSim2: A Cycle Accurate Memory System Simulator |
JNCA
2007
13 years 5 months ago
2007
As the line rates standards are changing frequently to provide higher bit rates, the routers design has become very challenging due to the need for new wire-speed router’s netwo...
RTAS
2005
IEEE
13 years 11 months ago
2005
IEEE
While caches have become invaluable for higher-end architectures due to their ability to hide, in part, the gap between processor speed and memory access times, caches (and partic...
PPOPP
1997
ACM
13 years 10 months ago
1997
ACM
Parallel algorithm designers need computational models that take first order system costs into account, but are also simple enough to use in practice. This paper introduces the L...
JUCS
2006
13 years 5 months ago
2006
Abstract: Advances in technology now make it possible to integrate hundreds of cores (e.g. general or special purpose processors, embedded memories, application specific components...
SIGOPS
2010
13 years 15 days ago
2010
Modern chip-level multiprocessors (CMPs) contain multiple processor cores sharing a common last-level cache, memory interconnects, and other hardware resources. Workloads running ...