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SBACPAD
2007
IEEE
121views Hardware» more  SBACPAD 2007»
10 years 10 months ago
DTA-C: A Decoupled multi-Threaded Architecture for CMP Systems
One way to exploit Thread Level Parallelism (TLP) is to use architectures that implement novel multithreaded execution models, like Scheduled DataFlow (SDF). This latter model pro...
Roberto Giorgi, Zdravko Popovic, Nikola Puzovic
MICRO
2005
IEEE
140views Hardware» more  MICRO 2005»
10 years 10 months ago
Dynamic Helper Threaded Prefetching on the Sun UltraSPARC CMP Processor
Data prefetching via helper threading has been extensively investigated on Simultaneous MultiThreading (SMT) or Virtual Multi-Threading (VMT) architectures. Although reportedly la...
Jiwei Lu, Abhinav Das, Wei-Chung Hsu, Khoa Nguyen,...
ISVLSI
2005
IEEE
95views VLSI» more  ISVLSI 2005»
10 years 10 months ago
System Level Methodology for Programming CMP Based Multi-Threaded Network Processor Architectures
Vijaykumar Ramamurthi, Jason McCollum, Christopher...
MICRO
2007
IEEE
168views Hardware» more  MICRO 2007»
10 years 10 months ago
Global Multi-Threaded Instruction Scheduling
Recently, the microprocessor industry has moved toward chip multiprocessor (CMP) designs as a means of utilizing the increasing transistor counts in the face of physical and micro...
Guilherme Ottoni, David I. August
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