4 search results - page 1 / 1 » DTA-C: A Decoupled multi-Threaded Architecture for CMP Syste... |
SBACPAD
2007
IEEE
13 years 10 months ago
2007
IEEE
One way to exploit Thread Level Parallelism (TLP) is to use architectures that implement novel multithreaded execution models, like Scheduled DataFlow (SDF). This latter model pro...
MICRO
2005
IEEE
13 years 10 months ago
2005
IEEE
Data prefetching via helper threading has been extensively investigated on Simultaneous MultiThreading (SMT) or Virtual Multi-Threading (VMT) architectures. Although reportedly la...
ISVLSI
2005
IEEE
13 years 10 months ago
2005
IEEE
MICRO
2007
IEEE
13 years 10 months ago
2007
IEEE
Recently, the microprocessor industry has moved toward chip multiprocessor (CMP) designs as a means of utilizing the increasing transistor counts in the face of physical and micro...