4 search results - page 1 / 1 » DVS for On-Chip Bus Designs Based on Timing Error Correction |
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
On-chip buses are typically designed to meet performance constraints at worst-case conditions, including process corner, temperature, IR-drop, and neighboring net switching patter...
DATE
2002
IEEE
13 years 9 months ago
2002
IEEE
As technology scales toward deep submicron, on-chip interconnects are becoming more and more sensitive to noise sources such as power supply noise, crosstalk, radiation induced ef...
MICRO
2003
IEEE
13 years 9 months ago
2003
IEEE
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
MSO
2003
13 years 5 months ago
2003
The use of sub-optimal digital systems can at times lead to high speed, efficient, costeffective structures that are sufficient to perform needed tasks. We describe here a system ...