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» Data Independence of Read, Write, and Control Structures in ...
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ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
13 years 10 months ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
DEBU
2010
152views more  DEBU 2010»
13 years 2 months ago
Implementing an Append-Only Interface for Semiconductor Storage
Solid-state disks are currently based on NAND flash and expose a standard disk interface. To accommodate limitations of the medium, solid-state disk implementations avoid rewritin...
Colin W. Reid, Philip A. Bernstein
ASPLOS
2010
ACM
13 years 8 months ago
Micro-pages: increasing DRAM efficiency with locality-aware data placement
Power consumption and DRAM latencies are serious concerns in modern chip-multiprocessor (CMP or multi-core) based compute systems. The management of the DRAM row buffer can signif...
Kshitij Sudan, Niladrish Chatterjee, David Nellans...
CLUSTER
2001
IEEE
13 years 9 months ago
Clusterfile: A Flexible Physical Layout Parallel File System
This paper presents Clusterfile, a parallel file system that provides parallel file access on a cluster of computers. Existing parallel file systems offer little control over matc...
Florin Isaila, Walter F. Tichy