10 search results - page 1 / 2 » Data Layout Transformation for Enhancing Data Locality on NU... |
IEEEPACT
2009
IEEE
13 years 11 months ago
2009
IEEE
—With increasing numbers of cores, future CMPs (Chip Multi-Processors) are likely to have a tiled architecture with a portion of shared L2 cache on each tile and a bankinterleave...
IPPS
1999
IEEE
13 years 8 months ago
1999
IEEE
In order to extract high levels of performance from modern parallel architectures, the effective management of deep memory hierarchies is very important. While architectural advan...
CC
2010
Springer
13 years 11 months ago
2010
Springer
On Chip Multiprocessors (CMP), it is common that multiple cores share certain levels of cache. The sharing increases the contention in cache and memory-to-chip bandwidth, further h...
SIGARCH
2008
13 years 4 months ago
2008
This paper presents a parallelization framework for emerging applications on the future chip multiprocessors (CMPs). With the continuing prevalence of CMP and the number of on-die...
IEEEPACT
1998
IEEE
13 years 8 months ago
1998
IEEE
Global locality analysis is a technique for improving the cache performance of a sequence of loop nests through a combination of loop and data layout optimizations. Pure loop tran...