71 search results - page 3 / 15 » Data Memory Design Considering Effective Bitwidth for Low-En... |
MTDT
2003
IEEE
13 years 11 months ago
2003
IEEE
Memory cores (especially SRAM cores) used on a system chip usually come from a memory compiler. Commercial memory compilers have their limitation— a large memory may need to be ...
DATE
1999
IEEE
13 years 10 months ago
1999
IEEE
This paper proposes a methodology to evaluate the effects of encodings on the power consumption of system-level buses in the presence of multi-level cache memories. The proposed m...
CODES
2002
IEEE
13 years 10 months ago
2002
IEEE
Limited energy and memory resources are important constraints in the design of an embedded system. Compression is an useful and widely employed mechanism to reduce the memory requ...
LCTRTS
2007
Springer
13 years 12 months ago
2007
Springer
As memory speeds and bus capacitances continue to rise, external memory bus power will make up an increasing portion of the total system power budget for system-on-a-chip embedded...
ISLPED
2005
ACM
13 years 11 months ago
2005
ACM
Tuning a configurable cache subsystem to an application can greatly reduce memory hierarchy energy consumption. Previous tuning methods use a level one configurable cache only, or...