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ICASSP
2011
IEEE
8 years 5 months ago
Data-path and memory error compensation technique for low power JPEG implementation
This paper presents a novel technique to mitigate effects of datapath and memory errors in JPEG implementations. These errors are mainly caused by voltage scaling and process vari...
Yunus Emre, Chaitali Chakrabarti
ICCD
2004
IEEE
138views Hardware» more  ICCD 2004»
9 years 10 months ago
Design and Implementation of Scalable Low-Power Montgomery Multiplier
In this paper, an efficient Montgomery multiplier is introduced for the modular exponentiation operation, which is fundamental to numerous public-key cryptosystems. Four aspects a...
Hee-Kwan Son, Sang-Geun Oh
SIPS
2007
IEEE
9 years 7 months ago
Design and Analysis of LDPC Decoders for Software Defined Radio
Low Density Parity Check (LDPC) codes are one of the most promising error correction codes that are being adopted by many wireless standards. This paper presents a case study for ...
Sangwon Seo, Trevor N. Mudge, Yuming Zhu, Chaitali...
ISCAS
2005
IEEE
167views Hardware» more  ISCAS 2005»
9 years 6 months ago
Low-power log-MAP turbo decoding based on reduced metric memory access
Due to the powerful error correcting performance, turbo codes have been adopted in many wireless communication standards. Although several low-power techniques have been proposed,...
Dong-Soo Lee, In-Cheol Park
DATE
2010
IEEE
158views Hardware» more  DATE 2010»
9 years 6 months ago
Energy- and endurance-aware design of phase change memory caches
—Phase change memory (PCM) is one of the most promising technology among emerging non-volatile random access memory technologies. Implementing a cache memory using PCM provides m...
Yongsoo Joo, Dimin Niu, Xiangyu Dong, Guangyu Sun,...
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