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» Datapath Scheduling using Dynamic Frequency Clocking
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DAC
2003
ACM
14 years 6 months ago
Pushing ASIC performance in a power envelope
Power dissipation is becoming the most challenging design constraint in nanometer technologies. Among various design implementation schemes, standard cell ASICs offer the best pow...
Ruchir Puri, Leon Stok, John M. Cohn, David S. Kun...
ISCA
2006
IEEE
169views Hardware» more  ISCA 2006»
13 years 11 months ago
Balanced Cache: Reducing Conflict Misses of Direct-Mapped Caches
Level one cache normally resides on a processor’s critical path, which determines the clock frequency. Directmapped caches exhibit fast access time but poor hit rates compared w...
Chuanjun Zhang
CODES
2005
IEEE
13 years 11 months ago
Power-smart system-on-chip architecture for embedded cryptosystems
In embedded cryptosystems, sensitive information can leak via timing, power, and electromagnetic channels. We introduce a novel power-smart system-on-chip architecture that provid...
Radu Muresan, Haleh Vahedi, Y. Zhanrong, Stefano G...
RTSS
2003
IEEE
13 years 11 months ago
Power-aware QoS Management in Web Servers
Power management in data centers has become an increasingly important concern. Large server installations are designed to handle peak load, which may be significantly larger than...
Vivek Sharma, Arun Thomas, Tarek F. Abdelzaher, Ke...
COMCOM
2006
126views more  COMCOM 2006»
13 years 5 months ago
Distributed and energy-efficient target localization and tracking in wireless sensor networks
In this paper, we propose and evaluate a distributed, energy-efficient, light-weight framework for target localization and tracking in wireless sensor networks. Since radio commun...
Jeongkeun Lee, Kideok Cho, Seungjae Lee, Taekyoung...