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» Delay Analysis of VLSI Interconnections Using the Diffusion ...
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VLSID
2004
IEEE
147views VLSI» more  VLSID 2004»
14 years 4 months ago
Computing Silent Gate Models for Noise Analysis from Slew and Delay Tables
Abstract--In this paper, we present a new approach to calculate the steady state resistance values for CMOS library gates. These resistances are defined as simple equivalent models...
Shabbir H. Batterywala, Narendra V. Shenoy
VLSID
2002
IEEE
91views VLSI» more  VLSID 2002»
14 years 4 months ago
Rational ABCD Modeling of High-Speed Interconnects
This paper introduces a new numerical approximation technique, called the Differential Quadrature Method (DQM), in order to derive the rational ABCD matrix representing the high-s...
Qinwei Xu, Pinaki Mazumder
ISPD
2003
ACM
110views Hardware» more  ISPD 2003»
13 years 9 months ago
Explicit gate delay model for timing evaluation
Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...
Muzhou Shao, Martin D. F. Wong, Huijing Cao, Youxi...
CDC
2009
IEEE
148views Control Systems» more  CDC 2009»
13 years 7 months ago
Input-output framework for robust stability of time-varying delay systems
The paper is devoted to the stability analysis of linear time varying delay. We first model the time varying delay system as an interconnected system between a known linear trans...
Yassine Ariba, Frédéric Gouaisbaut