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» Delay Test Quality Evaluation Using Bounded Gate Delays
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VTS
2007
IEEE
95views Hardware» more  VTS 2007»
13 years 10 months ago
Delay Test Quality Evaluation Using Bounded Gate Delays
: Conventionally, path delay tests are derived in a delay-independent manner, which causes most faults to be robustly untestable. Many non-robust tests are found but, in practice, ...
Soumitra Bose, Vishwani D. Agrawal
DATE
2003
IEEE
116views Hardware» more  DATE 2003»
13 years 9 months ago
Statistical Timing Analysis Using Bounds
The growing impact of within-die process variation has created the need for statistical timing analysis, where gate delays are modeled as random variables. Statistical timing anal...
Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sar...
MM
2004
ACM
106views Multimedia» more  MM 2004»
13 years 10 months ago
Probabilistic delay guarantees using delay distribution measurement
Carriers increasingly differentiate their wide-area connectivity offerings by means of customized services, such as virtual private networks (VPN) with Quality of Service (QoS) g...
Kartik Gopalan, Tzi-cker Chiueh, Yow-Jian Lin
ATS
2000
IEEE
134views Hardware» more  ATS 2000»
13 years 9 months ago
Fsimac: a fault simulator for asynchronous sequential circuits
At very high frequencies, the major potential of asynchronous circuits is absence of clock skew and, through that, better exploitation of relative timing relations. This paper pre...
Susmita Sur-Kolay, Marly Roncken, Ken S. Stevens, ...
DAC
2005
ACM
13 years 6 months ago
Circuit optimization using statistical static timing analysis
In this paper, we propose a new sensitivity based, statistical gate sizing method. Since circuit optimization effects the entire shape of the circuit delay distribution, it is dif...
Aseem Agarwal, Kaviraj Chopra, David Blaauw, Vladi...