424 search results - page 1 / 85 » Delay modelling improvement for low voltage applications |
EURODAC
1995
IEEE
13 years 7 months ago
1995
IEEE
Based on an explicit formulation of delays, an improved model for low voltage operation of CMOS inverter has been derived. Extrinsic and intrinsic effects, such as transistor curr...
ASPDAC
2006
ACM
13 years 10 months ago
2006
ACM
— Sakurai-Newton (SN) delay metric [1] is a widely used closed form delay metric for CMOS gates because of simplicity and reasonable accuracy. Nevertheless it can be shown that t...
ISQED
2010
IEEE
13 years 6 months ago
2010
IEEE
A new SRAM design is proposed. Body biasing improves the static noise margin (SNM) improved by at least 15% compared to the standard cells. Through using this technique, lowering ...
ITC
1996
IEEE
13 years 8 months ago
1996
IEEE
The detectability of delay flaws can be improved by testing CMOS IC's with a very low supply voltage -between 2 and 2.5 times the threshold voltage Vt of the transistors. A d...
SOCC
2008
IEEE
13 years 10 months ago
2008
IEEE
In this paper a new ultra low power SRAM cell is proposed. In the proposed SRAM topology, additional circuitry has been added to a standard 6T-SRAM cell to improve the static nois...