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VLSID
2006
IEEE
145views VLSI» more  VLSID 2006»
13 years 11 months ago
Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format
IEEE 754r is the ongoing revision to the IEEE 754 floating point standard and a major enhancement to the standard is the addition of decimal format. This paper proposes two novel ...
Himanshu Thapliyal, Saurabh Kotiyal, M. B. Sriniva...
DSD
2004
IEEE
104views Hardware» more  DSD 2004»
13 years 9 months ago
A Static Low-Power, High-Performance 32-bit Carry Skip Adder
In this paper, we present a full-static carry-skip adder designed to achieve low power dissipation and high-performance operation. To reduce the adder's delay and power consu...
Kai Chirca, Michael J. Schulte, John Glossner, Hao...
TC
1998
13 years 5 months ago
Multiple-Valued Signed-Digit Adder Using Negative Differential-Resistance Devices
—This paper describes a new signed-digit full adder (SDFA) circuit consisting of resonant-tunneling diodes (RTDs) and metal-oxide semiconductor field effect transistors (MOSFETs)...
Alejandro F. González, Pinaki Mazumder
PDPTA
2003
13 years 6 months ago
Quaternary Arithmetic Logic Unit on a Programmable Logic Device
Common binary arithmetic operations such as addition/subtraction and multiplication suffer from O(n) carry propagation delay where n is the number of digits. Carry lookahead helps...
Songpol Ongwattanakul, Phaisit Chewputtanagul, Dav...