86 search results - page 1 / 18 » Delay-Reduced Combinational Logic Synthesis using Multiplexe... |
CSREAESA
2006
13 years 5 months ago
2006
- This paper presents an approach to obtain reduced hardware and/or delay for synthesizing logic functions using multiplexers. Replication of single control line multiplexer is use...
DAC
2005
ACM
13 years 6 months ago
2005
ACM
This paper presents a novel synthesis algorithm that reduces the area needed for implementing multiplexers on an FPGA by an average of 18%. This is achieved by reducing the number...
DATE
2000
IEEE
13 years 8 months ago
2000
IEEE
Pass Transistor Logic has attracted more and more interest during last years, since it has proved to be an attractive alternative to static CMOS designs with respect to area, perf...
ICCAD
2009
IEEE
13 years 2 months ago
2009
IEEE
As CMOS devices are scaled down into the nanometer regime, concerns about reliability are mounting. Instead of viewing nanoscale characteristics as an impediment, technologies suc...
DAC
1996
ACM
13 years 8 months ago
1996
ACM
Technology mapping requires the unmapped logic network to be represented in terms of base functions, usually two-input NORs and inverters. Technology decomposition is the step tha...