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» Design and Analysis of On-Chip Networks for Large-Scale Cach...
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MICRO
2010
IEEE
153views Hardware» more  MICRO 2010»
9 years 7 months ago
Throughput-Effective On-Chip Networks for Manycore Accelerators
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...
Ali Bakhoda, John Kim, Tor M. Aamodt
IESS
2007
Springer
165views Hardware» more  IESS 2007»
10 years 3 months ago
Data Reuse Driven Memory and Network-On-Chip Co-Synthesis
NoCs present a possible communication infrastructure solution to deal with increased design complexity and shrinking time-to-market. The communication infrastructure is a signific...
Ilya Issenin, Nikil Dutt
ICMCS
2006
IEEE
149views Multimedia» more  ICMCS 2006»
10 years 3 months ago
Design and Implementation of a Multimedia Personalized Service Over Large Scale Networks
In this paper, we proposed to setup a distributed multimedia system which aggregates the capacity of multiple servers to provide customized multimedia services in a cost-effective...
Xiaorong Li, Terence Gih Guang, Bharadwaj Veeraval...
ICDCS
1998
IEEE
10 years 1 months ago
Using Leases to Support Server-Driven Consistency in Large-Scale Systems
This paper introduces volume leases as a mechanism for providing cache consistency for large-scale, geographically distributed networks. Volume leases are a variation of leases, w...
Jian Yin, Lorenzo Alvisi, Michael Dahlin, Calvin L...
GLVLSI
2006
IEEE
120views VLSI» more  GLVLSI 2006»
10 years 3 months ago
Sensitivity evaluation of global resonant H-tree clock distribution networks
A sensitivity analysis of resonant H-tree clock distribution networks is presented in this paper for a TSMC 0.18 μm CMOS technology. The analysis focuses on the effect of the dri...
Jonathan Rosenfeld, Eby G. Friedman
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