4 search results - page 1 / 1 » Design and Analysis of a New Self-Testing Adder which Utiliz... |
DDECS
2007
IEEE
13 years 11 months ago
2007
IEEE
— This paper describes a new self-testing 1-bit full adder. This circuit consists of three polymorphic NAND/NOR gates, two XOR gates and two inverters. The adder is able to detec...
CORR
2006
Springer
13 years 5 months ago
2006
Springer
Differential Power Analysis (DPA) presents a major challenge to mathematically-secure cryptographic protocols. Attackers can break the encryption by measuring the energy consumed i...
TC
1998
13 years 4 months ago
1998
—This paper describes a new signed-digit full adder (SDFA) circuit consisting of resonant-tunneling diodes (RTDs) and metal-oxide semiconductor field effect transistors (MOSFETs)...
DAC
2006
ACM
14 years 6 months ago
2006
ACM
A statistical model for the purpose of logic cell timing analysis in the presence of process variations is presented. A new current-based cell delay model is utilized, which can a...