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» Design and Evaluation of Data-Dependent Hardware for AES Enc...
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DAC
2001
ACM
14 years 7 months ago
Concurrent Error Detection of Fault-Based Side-Channel Cryptanalysis of 128-Bit Symmetric Block Ciphers
: Fault-based side channel cryptanalysis is very effective against symmetric and asymmetric encryption algorithms. Although straightforward hardware and time redundancy based concu...
Ramesh Karri, Kaijie Wu, Piyush Mishra, Yongkook K...
CHES
2007
Springer
154views Cryptology» more  CHES 2007»
14 years 7 days ago
Multi-gigabit GCM-AES Architecture Optimized for FPGAs
Abstract. This paper presents a design-space exploration of the Galois/Counter Mode (GCM) algorithm with Advanced Encryption Standard (AES) as underlying block cipher for high thro...
Stefan Lemsitzer, Johannes Wolkerstorfer, Norbert ...
DSD
2005
IEEE
104views Hardware» more  DSD 2005»
13 years 11 months ago
Design of Transport Triggered Architecture Processors for Wireless Encryption
Transport Triggered Architecture (TTA) offers a costeffective trade-off between the size and performance of ASICs and the programmability of general-purpose processors. In this pa...
Panu Hämäläinen, Jari Heikkinen, Ma...
FPL
2003
Springer
100views Hardware» more  FPL 2003»
13 years 11 months ago
Two Approaches for a Single-Chip FPGA Implementation of an Encryptor/Decryptor AES Core
In this paper we present a single-chip FPGA full encryptor/decryptor core design of the AES algorithm. Our design performs all of them, encryption, decryption and key scheduling pr...
Nazar A. Saqib, Francisco Rodríguez-Henr&ia...
ISSA
2004
13 years 7 months ago
High Data Rate 8-Bit Crypto Processor
This paper describes a high data rate 8-bit Crypto Processor based on Advanced Encryption Standard (Rijndael algorithm). Though the algorithm requires 32-bit wide data path but ou...
Sheikh Muhammad Farhan