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» Design and Evaluation of Hybrid Fault-Detection Systems
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ISCA
2005
IEEE
79views Hardware» more  ISCA 2005»
13 years 11 months ago
Design and Evaluation of Hybrid Fault-Detection Systems
As chip densities and clock rates increase, processors are becoming more susceptible to transient faults that can affect program correctness. Up to now, system designers have prim...
George A. Reis, Jonathan Chang, Neil Vachharajani,...
IPPS
2007
IEEE
13 years 11 months ago
FixD : Fault Detection, Bug Reporting, and Recoverability for Distributed Applications
Model checking, logging, debugging, and checkpointing/recovery are great tools to identify bugs in small sequential programs. The direct application of these techniques to the dom...
Cristian Tapus, David A. Noblet
AUTOMATICA
2006
68views more  AUTOMATICA 2006»
13 years 5 months ago
Relaxed fault detection and isolation: An application to a nonlinear case study
Given a number of possibly concurrent faults (and disturbances) that may affect a nonlinear dynamic system, it may not be possible to solve the standard fault detection and isolat...
Raffaella Mattone, Alessandro De Luca
ISCA
2000
IEEE
99views Hardware» more  ISCA 2000»
13 years 9 months ago
Transient fault detection via simultaneous multithreading
Smaller feature sizes, reduced voltage levels, higher transistor counts, and reduced noise margins make future generations of microprocessors increasingly prone to transient hardw...
Steven K. Reinhardt, Shubhendu S. Mukherjee
EDCC
2006
Springer
13 years 9 months ago
SEU Mitigation Techniques for Microprocessor Control Logic
The importance of fault tolerance at the processor architecture level has been made increasingly important due to rapid advancements in the design and usage of high performance de...
T. S. Ganesh, Viswanathan Subramanian, Arun K. Som...