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MICRO
2003
IEEE
161views Hardware» more  MICRO 2003»
13 years 9 months ago
Design and Implementation of High-Performance Memory Systems for Future Packet Buffers
In this paper we address the design of a future high-speed router that supports line rates as high as OC-3072 (160 Gb/s), around one hundred ports and several service classes. Bui...
Jorge García-Vidal, Jesús Corbal, Ll...
HOTI
2005
IEEE
13 years 10 months ago
Design of Randomized Multichannel Packet Storage for High Performance Routers
High performance routers require substantial amounts of memory to store packets awaiting transmission, requiring the use of dedicated memory devices with the density and capacity ...
Sailesh Kumar, Patrick Crowley, Jonathan S. Turner
ICS
2011
Tsinghua U.
12 years 8 months ago
Hystor: making the best use of solid state drives in high performance storage systems
With the fast technical improvement, flash memory based Solid State Drives (SSDs) are becoming an important part of the computer storage hierarchy to significantly improve perfo...
Feng Chen, David A. Koufaty, Xiaodong Zhang
ISCA
2009
IEEE
239views Hardware» more  ISCA 2009»
13 years 11 months ago
Scalable high performance main memory system using phase-change memory technology
The memory subsystem accounts for a significant cost and power budget of a computer system. Current DRAM-based main memory systems are starting to hit the power and cost limit. A...
Moinuddin K. Qureshi, Vijayalakshmi Srinivasan, Ju...
ISCA
2012
IEEE
279views Hardware» more  ISCA 2012»
11 years 6 months ago
Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems
When multiple processor (CPU) cores and a GPU integrated together on the same chip share the off-chip main memory, requests from the GPU can heavily interfere with requests from t...
Rachata Ausavarungnirun, Kevin Kai-Wei Chang, Lava...