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» Design and Implementation of Power-Aware Virtual Memory
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ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
13 years 9 months ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
TC
2011
12 years 11 months ago
Energy Reduction in Consolidated Servers through Memory-Aware Virtual Machine Scheduling
—Increasing energy consumption in server consolidation environments leads to high maintenance costs for data centers. Main memory, no less than processor, is a major energy consu...
Jae-Wan Jang, Myeongjae Jeon, Hyo-Sil Kim, Heeseun...
USENIX
2007
13 years 7 months ago
Virtual Machine Memory Access Tracing with Hypervisor Exclusive Cache
Virtual machine (VM) memory allocation and VM consolidation can benefit from the prediction of VM page miss rate at each candidate memory size. Such prediction is challenging for...
Pin Lu, Kai Shen
CLEIEJ
2002
113views more  CLEIEJ 2002»
13 years 4 months ago
The MT Stack: Paging Algorithm and Performance in a Distributed Virtual Memory System
Advances in parallel computation are of central importance to Artificial Intelligence due to the significant amount of time and space their programs require. Functional languages ...
Marco T. Morazán, Douglas R. Troeger, Myles...
MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
13 years 10 months ago
Virtually Pipelined Network Memory
We introduce virtually-pipelined memory, an architectural technique that efficiently supports high-bandwidth, uniform latency memory accesses, and high-confidence throughput eve...
Banit Agrawal, Timothy Sherwood