164 search results - page 33 / 33 » Design and Implementation of the Memory Scheduler for the PC... |
ISCA
2000
IEEE
13 years 9 months ago
2000
IEEE
Our program benchmarks and simulations of novel circuits indicate that large-window processors are feasible. Using our redesigned superscalar components, a large-window processor ...
SPAA
1997
ACM
13 years 9 months ago
1997
ACM
Pipelining has been used in the design of many PRAM algorithms to reduce their asymptotic running time. Paul, Vishkin, and Wagener (PVW) used the approach in a parallel implementat...
DSD
2009
IEEE
14 years 5 days ago
2009
IEEE
Abstract—Verification of application requirements is becoming a bottleneck in system-on-chip design, as the number of applications grows. Traditionally, the verification comple...
ISCA
2010
IEEE
13 years 10 months ago
2010
IEEE
Given the multicore microprocessor revolution, we argue that the architecture research community needs a dramatic increase in simulation capacity. We believe FPGA Architecture Mod...