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ANCS
2009
ACM
13 years 1 months ago
Design and performance analysis of a DRAM-based statistics counter array architecture
The problem of maintaining efficiently a large number (say millions) of statistics counters that need to be updated at very high speeds (e.g. 40 Gb/s) has received considerable re...
Haiquan (Chuck) Zhao, Hao Wang, Bill Lin, Jun (Jim...
CF
2009
ACM
13 years 10 months ago
Core monitors: monitoring performance in multicore processors
As we reach the limits of single-core computing, we are promised more and more cores in our systems. Modern architectures include many performance counters per core, but few or no...
Paul E. West, Yuval Peress, Gary S. Tyson, Sally A...
DAC
2008
ACM
14 years 4 months ago
Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array fo
: Spin-Torque Transfer Magnetic RAM (STT MRAM) is a promising candidate for future universal memory. It combines the desirable attributes of current memory technologies such as SRA...
Jing Li, Charles Augustine, Sayeef S. Salahuddin, ...
BMCBI
2004
113views more  BMCBI 2004»
13 years 3 months ago
Leveraging two-way probe-level block design for identifying differential gene expression with high-density oligonucleotide array
Background: To identify differentially expressed genes across experimental conditions in oligonucleotide microarray experiments, existing statistical methods commonly use a summar...
Leah Barrera, Chris Benner, Yong-Chuan Tao, Elizab...
DAC
2004
ACM
14 years 4 months ago
Statistical optimization of leakage power considering process variations using dual-Vth and sizing
timing analysis tools to replace standard deterministic static timing analyzers whereas [8,27] develop approaches for the statistical estimation of leakage power considering within...
Ashish Srivastava, Dennis Sylvester, David Blaauw