788 search results - page 1 / 158 » Design and use of a system-level specification and verificat... |
CODES
2010
IEEE
13 years 2 months ago
2010
IEEE
The impact of process variation in state of the art technology makes traditional (worst case) designs unnecessarily pessimistic, which translates to suboptimal designs in terms of...
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
EURODAC
1994
IEEE
13 years 8 months ago
1994
IEEE
EUROMICRO
1999
IEEE
13 years 8 months ago
1999
IEEE
Software synthesis for system level design languages becomes feasible because the current technology, pricing and application trends will most likely alleviate the industrial empha...
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
Automated synthesis of monitors from high-level properties plays a significant role in assertion-based verification. We present here a methodology to synthesize assertion monitors...