2 search results - page 1 / 1 » Design closure driven delay relaxation based on convex cost ... |
DATE
2007
IEEE
13 years 10 months ago
2007
IEEE
Design closure becomes hard to achieve at physical layout stage due to the emergence of long global interconnects. Consequently, interconnect planning needs to be integrated in hi...
DAC
2000
ACM
14 years 5 months ago
2000
ACM
This paper presents MINFLOTRANSIT, a new transistor sizing tool for fast sizing of combinational circuits with minimal cost. MINFLOTRANSIT is an iterative relaxation based tool th...