59 search results - page 12 / 12 » Design for Verification in System-level Models and RTL |
EMSOFT
2006
Springer
13 years 9 months ago
2006
Springer
Upper bounds on worst-case execution times, which are commonly called WCET, are a prerequisite for validating the temporal correctness of tasks in a real-time system. Due to the e...
IFIP
2001
Springer
13 years 10 months ago
2001
Springer
— Semi-formal verification based on symbolic simulation offers a good compromise between formal model checking and numerical simulation. The generation of functional test vector...
DAC
2004
ACM
14 years 6 months ago
2004
ACM
The increasing complexity of today's mixed-signal integrated circuits necessitates both top-down and bottom-up system-level verification. Time-domain state-space modeling and...
DAC
2008
ACM
14 years 6 months ago
2008
ACM
Driven by increasing complexity and reliability demands, the Japanese Aerospace Exploration Agency (JAXA) in 2004 commissioned development of ELEGANT, a complete SpecC-based envir...