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ASPDAC
1995
ACM
130views Hardware» more  ASPDAC 1995»
10 years 4 months ago
Design for testability using register-transfer level partial scan selection
Abstract - An approach to top down design for testability using register-transfer level(RTL) partial scan selection is described. We propose a scan selection technique based on tes...
Akira Motohara, Sadami Takeoka, Toshinori Hosokawa...
DAC
1994
ACM
10 years 5 months ago
Optimizing Resource Utilization and Testability Using Hot Potato Techniques
This paper introduces hot potato high level synthesis transformation techniques. These techniques add deflection operations in a computation in such a way that a specific goal is ...
Miodrag Potkonjak, Sujit Dey
ICCAD
1996
IEEE
121views Hardware» more  ICCAD 1996»
10 years 5 months ago
Identification of unsettable flip-flops for partial scan and faster ATPG
State justification is a time-consuming operation in test generation for sequential circuits. In this paper, we present a technique to rapidly identify state elements (flip-flops)...
Ismed Hartanto, Vamsi Boppana, W. Kent Fuchs
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