3 search results - page 1 / 1 » Design of On-chip and Off-chip Interfaces for a GALS NoC Arc... |
ASYNC
2006
IEEE
13 years 11 months ago
2006
IEEE
DATE
2010
IEEE
13 years 10 months ago
2010
IEEE
There is today little doubt on the fact that a high-performance and cost-effective Network-on-Chip can only be designed in 45nm and beyond under a relaxed synchronization assumpti...
ISVLSI
2008
IEEE
13 years 11 months ago
2008
IEEE
The evolution of deep submicron technologies allows the development of increasingly complex Systems on a Chip (SoC). However, this evolution is rendering less viable some well-est...