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ANCS
2007
ACM
13 years 9 months ago
Ruler: high-speed packet matching and rewriting on NPUs
Programming specialized network processors (NPU) is inherently difficult. Unlike mainstream processors where architectural features such as out-of-order execution and caches hide ...
Tomas Hruby, Kees van Reeuwijk, Herbert Bos
SAMOS
2004
Springer
13 years 10 months ago
Scalable Instruction-Level Parallelism.
This paper presents a model for instruction-level distributed computing that allows the implementation of scalable chip multiprocessors. Based on explicit microthreading it serves ...
Chris R. Jesshope
VLDB
2001
ACM
109views Database» more  VLDB 2001»
13 years 9 months ago
Analyzing energy behavior of spatial access methods for memory-resident data
The proliferation of mobile and pervasive computing devices has brought energy constraints into the limelight, together with performance considerations. Energy-conscious design is...
Ning An, Anand Sivasubramaniam, Narayanan Vijaykri...
ISCA
2010
IEEE
336views Hardware» more  ISCA 2010»
13 years 9 months ago
Reducing cache power with low-cost, multi-bit error-correcting codes
Technology advancements have enabled the integration of large on-die embedded DRAM (eDRAM) caches. eDRAM is significantly denser than traditional SRAMs, but must be periodically r...
Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chisht...
RTCSA
2006
IEEE
13 years 11 months ago
objSampler: A Ubiquitous Logging Tool for Recording Encounters with Real World Objects
We propose a novel tool, called objSampler, with which users can record and recall “encounters” with objects in ubiquitous computing environments. We encounter various things,...
Jun'ichi Yura, Hideaki Ogawa, Taizo Zushi, Jin Nak...