Sciweavers

50 search results - page 10 / 10
» Design of a Gigabit ATM Switch
Sort
View
DAC
2001
ACM
14 years 5 months ago
LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs
This paper presents LOTTERYBUS, a novel high-performance communication architecture for system-on-chip (SoC) designs. The LOTTERYBUS architecture was designed to address the follo...
Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshmi...
CHES
2000
Springer
75views Cryptology» more  CHES 2000»
13 years 9 months ago
A 155 Mbps Triple-DES Network Encryptor
The presented Triple-DES encryptor is a single-chip solution to encrypt network communication. It is optimized for throughput and fast switching between virtual connections like fo...
Herbert Leitold, Wolfgang Mayerwieser, Udo Payer, ...
DSD
2009
IEEE
118views Hardware» more  DSD 2009»
13 years 11 months ago
Internet-Router Buffered Crossbars Based on Networks on Chip
—The scalability and performance of the Internet depends critically on the performance of its packet switches. Current packet switches are based on single-hop crossbar fabrics, w...
Kees Goossens, Lotfi Mhamdi, Iria Varela Senin
ICMCS
2000
IEEE
115views Multimedia» more  ICMCS 2000»
13 years 9 months ago
Common Time Reference for Interactive Multimedia Applications
A delay of about 100 ms gives human communicators the feeling of live interaction. Since in a global network the propagation delay alone is about 100 ms, every other delay compone...
Mario Baldi, Yoram Ofek
INFOCOM
2002
IEEE
13 years 9 months ago
Restoration Algorithms for Virtual Private Networks in the Hose Model
—A Virtual Private Network (VPN) aims to emulate the services provided by a private network over the shared Internet. The endpoints of e connected using abstractions such as Virt...
Giuseppe F. Italiano, Rajeev Rastogi, Bülent ...