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CSREAESA
2003
13 years 6 months ago
Static Pattern Predictor (SPP) Based Low Power Instruction Cache Design
Energy dissipation in cache memories is becoming a major design issue in embedded microprocessors. Predictive filter cache based instruction cache hierarchy is effective in reduci...
Kugan Vivekanandarajah, Thambipillai Srikanthan, C...
JCP
2007
181views more  JCP 2007»
13 years 5 months ago
Reducing Energy Consumption of Wireless Sensor Networks through Processor Optimizations
When the environmental conditions are stable, a typical Wireless Sensor Network (WSN) application may sense and process very similar or constant data values for long durations. Thi...
Gürhan Küçük, Can Basaran
VLSID
2002
IEEE
114views VLSI» more  VLSID 2002»
13 years 10 months ago
Minimizing Energy Consumption for High-Performance Processing
Power consumption is becoming an increasingly important constraint in the design of microprocessors. This paper examines the use of multiple constrained processors running at lowe...
Eric F. Weglarz, Kewal K. Saluja, Mikko H. Lipasti
HPCA
2008
IEEE
14 years 5 months ago
EXCES: External caching in energy saving storage systems
Power consumption within the disk-based storage subsystem forms a substantial portion of the overall energy footprint in commodity systems. Researchers have proposed external cach...
Luis Useche, Jorge Guerra, Medha Bhadkamkar, Mauri...
PACS
2000
Springer
99views Hardware» more  PACS 2000»
13 years 9 months ago
Dynamically Reconfiguring Processor Resources to Reduce Power Consumption in High-Performance Processors
Power dissipation is a major concern not only for portable systems, but also for high-performance systems. In the past, energy consumption and processor heating was reduced mainly...
Roberto Maro, Yu Bai, R. Iris Bahar