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VLSISP
2008
95views more  VLSISP 2008»
13 years 4 months ago
Design of an H.264/AVC Decoder with Memory Hierarchy and Line-Pixel-Lookahead
This paper describes a novel memory hierarchy and line-pixel-lookahead (LPL) for an H.264/AVC video decoder. The memory system is the bottleneck of most video processors, particula...
Tsu-Ming Liu, Chen-Yi Lee
TVLSI
2008
117views more  TVLSI 2008»
13 years 4 months ago
Configurable VLSI Architecture for Deblocking Filter in H.264/AVC
In this paper, we study and analyze the computational complexity of the deblocking filter in H.264/AVC baseline decoder based on SimpleScalar/ARM simulator. The simulation result s...
Chung-Ming Chen, Chung-Ho Chen
ASPDAC
2006
ACM
178views Hardware» more  ASPDAC 2006»
13 years 10 months ago
Hardware architecture design of an H.264/AVC video codec
Abstract—H.264/AVC is the latest video coding standard. It significantly outperforms the previous video coding standards, but the extraordinary huge computation complexity and m...
Tung-Chien Chen, Chung-Jr Lian, Liang-Gee Chen
ASPDAC
2006
ACM
140views Hardware» more  ASPDAC 2006»
13 years 10 months ago
A near optimal deblocking filter for H.264 advanced video coding
- We propose a near optimal hardware architecture for deblocking filter in H.264/MPEG-4 AVC. We propose a novel filtering order and a data reuse strategy that result in significant...
Shen-Yu Shih, Cheng-Ru Chang, Youn-Long Lin
ICASSP
2011
IEEE
12 years 8 months ago
Joint algorithm-architecture optimization of CABAC to increase speed and reduce area cost
To address the increasing demand for higher resolution and frame rates, processing speed (i.e. performance) and area cost need to be considered in the development of next generati...
Vivienne Sze, Anantha P. Chandrakasan