Sciweavers

3 search results - page 1 / 1
» Design optimization for single-event upset robustness using ...
Sort
View
ICCAD
2006
IEEE
141views Hardware» more  ICCAD 2006»
14 years 1 months ago
Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques
An optimization algorithm for the design of combinational circuits that are robust to single-event upsets (SEUs) is described. A simple, highly accurate model for the SEU robustne...
Mihir R. Choudhury, Quming Zhou, Kartik Mohanram
PATMOS
2007
Springer
13 years 11 months ago
Soft Error-Aware Power Optimization Using Gate Sizing
—Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the...
Foad Dabiri, Ani Nahapetian, Miodrag Potkonjak, Ma...
TASE
2008
IEEE
13 years 4 months ago
Randomized Optimal Design of Parallel Manipulators
This work intends to deal with the optimal kinematic synthesis problem of parallel manipulators under a unified framework. Observing that regular (e.g., hyper-rectangular) workspac...
Yunjiang Lou, Guanfeng Liu, Zexiang Li