125 search results - page 3 / 25 » Design space minimization with timing and code size optimiza... |
ISSS
2002
IEEE
13 years 10 months ago
2002
IEEE
Software pipelining and unfolding are commonly used techniques to increase parallelism for DSP applications. However, these techniques expand the code size of the application sign...
SCOPES
2004
Springer
13 years 11 months ago
2004
Springer
Digital signal processing applications are implemented in embedded systems with fixed-point arithmetic to minimize the cost and the power consumption. To reduce the application ti...
LCTRTS
2010
Springer
13 years 7 months ago
2010
Springer
DSP processors usually provide dedicated address generation units (AGUs) to assist address computation. By carefully allocating variables in the memory, DSP compilers take advanta...
MICRO
2002
IEEE
13 years 10 months ago
2002
IEEE
Multimedia processing on embedded devices requires an architecture that leads to high performance, low power consumption, reduced design complexity, and small code size. In this p...
RTCSA
2007
IEEE
13 years 12 months ago
2007
IEEE
Code optimization of the offset assignment generated in embedded systems allows for power and space efficient systems. We propose a new heuristic that uses edge classification to ...