63 search results - page 3 / 13 » Designing High Bandwidth On-Chip Caches |
ISCAPDCS
2004
13 years 7 months ago
2004
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past de...
MICRO
1999
IEEE
13 years 10 months ago
1999
IEEE
This paper studies an interesting yet less explored behavior of memory access instructions, called access region locality. Unlike the traditional temporal and spatial data localit...
ISCA
1998
IEEE
13 years 10 months ago
1998
IEEE
Modern cache designs exploit spatial locality by fetching large blocks of data called cache lines on a cache miss. Subsequent references to words within the same cache line result...
ISCA
1997
IEEE
13 years 10 months ago
1997
IEEE
The effectiveness of texture mapping in enhancing the realism of computer generated imagery has made support for real-time texture mapping a critical part of graphics pipelines. D...
MICRO
2006
IEEE
14 years 1 days ago
2006
IEEE
Recently-proposed processor microarchitectures for high Memory Level Parallelism (MLP) promise substantial performance gains. Unfortunately, current cache hierarchies have Miss-Ha...