83 search results - page 1 / 17 » Designing Reliable Algorithms in Unreliable Memories |
ESA
2005
Springer
13 years 9 months ago
2005
Springer
DAC
2009
ACM
13 years 9 months ago
2009
ACM
Process scaling has given designers billions of transistors to work with. As feature sizes near the atomic scale, extensive variation and wearout inevitably make margining unecono...
PODC
2003
ACM
13 years 9 months ago
2003
ACM
We consider the model of unreliable network links, where at each time unit a link might be either up or down. We consider two related problems. The first, establishing end to end...
ICCD
2006
IEEE
14 years 1 months ago
2006
IEEE
— As the geometries of the transistors reach the physical limits of operation, one of the main design challenges of Systems-on-Chips (SoCs) will be to provide dynamic (run-time) ...
ICDCS
2006
IEEE
13 years 10 months ago
2006
IEEE
This paper presents a design and analysis of scheduling techniques to cope with the inherent unreliability and instability of worker nodes in large-scale donation-based distribute...