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SAMOS
2004
Springer
13 years 10 months ago
Scalable Instruction-Level Parallelism.
This paper presents a model for instruction-level distributed computing that allows the implementation of scalable chip multiprocessors. Based on explicit microthreading it serves ...
Chris R. Jesshope
ISCA
2005
IEEE
181views Hardware» more  ISCA 2005»
13 years 11 months ago
Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors
With the ability to place large numbers of transistors on a single silicon chip, manufacturers have begun developing chip multiprocessors (CMPs) containing multiple processor core...
Evan Speight, Hazim Shafi, Lixin Zhang, Ramakrishn...
CCE
2006
13 years 5 months ago
Modeling and temperature control of rapid thermal processing
In the past few years, Rapid Thermal Processes (RTP) have gained acceptance as mainstream technology for semi-conductors manufacturing. These processes are characterized by a sing...
Eyal Dassau, Benyamin Grosman, Daniel R. Lewin