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MICRO
2006
IEEE
105views Hardware» more  MICRO 2006»
13 years 10 months ago
Distributed Microarchitectural Protocols in the TRIPS Prototype Processor
Growing on-chip wire delays will cause many future microarchitectures to be distributed, in which hardware resources within a single processor become nodes on one or more switched...
Karthikeyan Sankaralingam, Ramadass Nagarajan, Rob...
ISCA
2008
IEEE
92views Hardware» more  ISCA 2008»
13 years 11 months ago
Counting Dependence Predictors
Modern processors rely on memory dependence prediction to execute load instructions as early as possible, speculating that they are not dependent on an earlier, unissued store. To...
Franziska Roesner, Doug Burger, Stephen W. Keckler
HPCA
2003
IEEE
14 years 5 months ago
Active I/O Switches in System Area Networks
We present an active switch architecture to improve the performance of systems connected via system area networks. Our programmable active switches not only flexibly route packets...
Ming Hao, Mark Heinrich
SPAA
2006
ACM
13 years 10 months ago
Modeling instruction placement on a spatial architecture
In response to current technology scaling trends, architects are developing a new style of processor, known as spatial computers. A spatial computer is composed of hundreds or eve...
Martha Mercaldi, Steven Swanson, Andrew Petersen, ...
INFOCOM
2008
IEEE
13 years 11 months ago
Run-Time System for Scalable Network Services
Sophisticated middlebox services–such as network monitoring and intrusion detection, DDoS mitigation, worm scanning, XML parsing and protocol transformation–are becoming incre...
Upendra Shevade, Ravi Kokku, Harrick M. Vin