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» Divide-and-Conquer IDDQ Testing for Core-Based System Chips
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VLSID
2002
IEEE
131views VLSI» more  VLSID 2002»
14 years 4 months ago
Divide-and-Conquer IDDQ Testing for Core-Based System Chips
IDDQ testing has been used as a test technique to supplement voltage testing of CMOS chips. The idea behind IDDQ testing is to declare a chip as faulty if the steady-state current...
C. P. Ravikumar, Rahul Kumar
ET
2002
115views more  ET 2002»
13 years 4 months ago
CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing
As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CASBUS that solves ...
Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki
ITC
1997
IEEE
73views Hardware» more  ITC 1997»
13 years 8 months ago
A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems
In a fundamental paradigm shift in system design, entire systems are being built on a single chip, using multiple embedded cores. Though the newest system design methodology has s...
Indradeep Ghosh, Niraj K. Jha, Sujit Dey
DAC
1999
ACM
13 years 8 months ago
Microprocessor Based Testing for Core-Based System on Chip
The purpose of this paper is to develop a exible design for test methodology for testing a core-based system on chip SOC. The novel feature of the approach is the use an embedde...
Christos A. Papachristou, F. Martin, Mehrdad Noura...
DFT
1997
IEEE
93views VLSI» more  DFT 1997»
13 years 8 months ago
An IDDQ Sensor for Concurrent Timing Error Detection
Abstract— Error control is a major concern in many computer systems, particularly those deployed in critical applications. Experience shows that most malfunctions during system o...
Christopher G. Knight, Adit D. Singh, Victor P. Ne...