29 search results - page 1 / 6 » Dynamic Co-Processor Architecture for Software Acceleration ... |
ICCD
2006
IEEE
14 years 1 months ago
2006
IEEE
By integrating one or more (hard or soft) CPU core on the chip, new generation platform FPGAs have become configurable systems on a chip (CSoC) that support a combined software an...
DSD
2011
IEEE
12 years 4 months ago
2011
IEEE
Abstract—We present a new low-level interfacing scheme for connecting custom accelerators to processors that tolerates latencies that usually occur when accessing hardware accele...
SIGOPS
2011
12 years 11 months ago
2011
While application performance and power-efficiency are both important, application correctness is even more important. In other words, if the application is misbehaving, it is li...
TVLSI
2002
13 years 4 months ago
2002
Abstract--Hardward/software (HW/SW) codesign and reconfigurable computing are commonly used methodologies for digitalsystems design. However, no previous work has been carried out ...
ISPASS
2010
IEEE
13 years 11 months ago
2010
IEEE
—While many-core accelerator architectures, such as today’s Graphics Processing Units (GPUs), offer orders of magnitude more raw computing power than contemporary CPUs, their m...