This article describes an emulation-based method for locating stuck-at faults in combinational and synchronous sequential circuits. The method is based on automatically designing a...
Abstract— Substantial attention is being paid to the fault diagnosis problem in recent test literature. Yet, the compaction of test vectors for fault diagnosis is little explored...
Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahas...
We describe a method for designing fault tolerant circuits based on an extension of a Concurrent Error Detection (CED) technique. The proposed extension combines parity check code...
A deductive technique is presented that uses voltage testing for the diagnosis of single bridging faults between two gate input or output lines and is applicable to combinational ...
We present a fast, dynamic fault coverage estimation technique for sequential circuits that achieves high degrees of accuracy by signi cantly reducing the number of injected fault...